1. Field
Embodiments of the inventive concept relate to a fuse data reading circuit and, more particularly, to a fuse data reading circuit configured to read fuse data in multiple reading modes.
2. Description of Related Art
Due to the integration of memory cells with a large memory capacity into semiconductor memory devices, the amount of information preset and stored to determine the operating environment of the semiconductor memory devices has also increased. Fuse circuits may typically be used to store various pieces of information that determine the operation of the semiconductor memory devices.
For example, redundancy information regarding a defective memory cell (e.g., addresses of defective memory cells), direct-current (DC)-level trimming information and mode-register set (MRS) information regarding a semiconductor memory device may be stored in the fuse circuit. The MRS information may be used by the semiconductor memory device to control an internal operation. The MRS information stored in the fuse circuit may also be read by an external device, such as a memory controller, to control operation of the semiconductor memory device. In an alternative embodiment, other semiconductor devices may include the fuse circuit other than a semiconductor memory device.
A laser fuse, an electrical fuse, or an anti-fuse circuit may be employed as the fuse circuit. Connection of the laser fuse may be controlled with the irradiation of laser beams, and connection of the electrical fuse may be controlled with the application of electrical signals. An anti-fuse circuit (which also may be either a laser fuse or electrical fuse) may make the transition from a high-resistance state to a low-resistance state after being subject to a laser or an electrical signal.
The fuse circuit may be read during a power-up step. When an external voltage is initially applied to a semiconductor memory device, a power-up signal configured to drive the semiconductor memory device in response to the external voltage may be generated, and the operation of reading the fuse circuit may be enabled simultaneously with generation of a clock signal synchronized with the power-up signal.
In this case, after enabling the reading operation, output voltages of DC circuits of the semiconductor memory device may be put into unstable states, and a predetermined amount of time may be required to stabilize the output voltages of the DC circuits.
When the operation of reading the fuse circuit is performed under the same sensing conditions (e.g., a sensing voltage and/or a clock frequency) during normal device operation reading periods, although sufficient sensitivity may be provided during certain times (e.g., during certain environments), reading errors of the fuse data may occur at other times due to insufficient sensitivity (e.g., during an unstable environments). As a result, the semiconductor memory device may suffer from operating errors.